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ISL96017
Data Sheet April 17, 2006 FN8243.1
128-Tap DCP, 16kbit EEPROM, and I2C Serial Interface
This device integrates a 128-tap digitally controlled potentiometer, 16kbit of EEPROM, and a 2-wire I2C serial interface. The device is powered by a single 3.3V supply. The potentiometer is available with total resistance of either 10k or 50k. The memory is organized in 128 pages of 16 bytes each, to reduce total programming time. All programming signals are generated on-chip. The potentiometer is implemented with a combination of CMOS switches and resistor elements. The position of the wiper can be stored in non-volatile memory and then be recalled upon a subsequent power-up. The three terminals of the potentiometer are available for use as either a variable resistor or a resistor divider.
Features
* Integrated Digitally Controlled Potentiometer - 128-Tap Positions - 10k, 50k Total Resistance - Monotonic Over Temperature - Non-Volatile Wiper Position Storage - 0 to VDD Terminal Voltage * I2C Serial Interface * 16kbit EEPROM - 50 Years Retention @ 55C - 1,000,000 Cycles Endurance * Single 3.3 0.3V Supply * 3mm x 3mm Thin DFN Package - 0.8mm Max Thickness, 0.65mm Pitch * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL96017 (8 LD TDFN) TOP VIEW
RH 1 RW 2 RL 3 VDD 4
8 WP 7 SCL 6 SDA 5 GND
Ordering Information
PART NUMBER ISL96017WIRT8Z* (Note) ISL96017UIRT8Z* (Note) PART MARKING 96017WIZ 96017UIZ RTOTAL (k) 10 50 TEMP. RANGE (C) -40 to 85 -40 to 85 PACKAGE 8 Ld 3x3 TDFN (Pb-free) 8 Ld 3x3 TDFN (Pb-free) PKG. DWG. # L8.3x3A L8.3x3A
*Add "-TK" suffix for 1000 units tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL96017 Block Diagram
SDA
16kbit EEPROM POWER-UP, INTERFACE, AND CONTROL LOGIC
SCL
RH
WP
RW
RL
Pin Descriptions
PIN 1 2 3 4 5 6 7 8 SYMBOL RH RW RL VDD GND SDA SCL WP "High" terminal of the DCP "Wiper" terminal of the DCP "Low" terminal of the DCP Power supply Ground Open drain serial interface data input/output Open drain serial interface clock input Hardware write protection pin. Active low. Prevents any "Write" operation to the device. DESCRIPTION
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ISL96017
Absolute Maximum Ratings
Storage Temperature: . . . . . . . . . . . . . . . . . . . . . . . .-65C to 150C Note: All Voltages with Respect to GND Voltage at SCL, SDA, WP: . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V Voltage at RH, RW, RL: . . . . . . . . . . . . . . . . . . . . . . . GND to VDD VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V Lead Temperature (Soldering, 10s): . . . . . . . . . . . . . . . . . . . . 300C Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA ESD (MIL-STD-883B, Method 3014) . . . . . . . . . . . . . . . . . . .>2000V ESD (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150V
Thermal Information
Thermal Resistance (Typical, Note 1) JA 8 Ld TDFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90(C/W) Moisture Sensitivity (see Technical Brief TB363). . . . . . . . . .Level 2 Maximum Junction Temperature (Plastic Package). . . . . . . . . .150C
Recommended Operating Conditions
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C VDD Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 3.0V to 3.6V Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device, at these or any other conditions above those listed in the operational sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 for details.
Electrical Specifications Over recommended operating conditions unless otherwise stated. All voltages with respect to GND.
SYMBOL IccdSby IccdRd IccdWr ILkgDig ILkgDCP VDDRamp tDCP (Note 13) tD PARAMETER Standby Current at VDD Read Current at VDD Write Current at VDD Leakage Current at Pins SDA, SCL, and WP Leakage Current at RH, RW, RL VDD Power-Up Ramp Rate DCP Wiper Response Time Power-Up Delay SCL falling edge of last bit of DCP Data Byte to wiper change VDD above 2.6V, to DCP Initial Value Register recall completed, and I2C Interface in standby state 10 W and U versions, respectively. TA = 25C. Measured between RH and RL pins. TA = 25C. Measured between RH and RL pins. VDD = 3.3V @ 25C. Wiper current = VDD/RTotal 7 -20 100 10, 50 20 300 TEST CONDITIONS Serial interface in standby Reading with 400kHz at SCL Writing to EEPROM Pin voltage from GND to VDD Pin voltage from GND to VDD -10 -1 0.2 1.5 3 MIN TYP (Note 1) MAX 10 1 5 10 1 UNIT A mA mA A A V/ms s ms
CH/CW/CL (Note 13) RTotal
RH, RW, RL Pin Capacitance Total Resistance RTotal Tolerance
pF k % Bits
RWiper
Wiper Resistance DCP Resolution
DCP IN VOLTAGE DIVIDER MODE (0V at RL, VCC at RH; measured at RW unloaded) FSerror (Note 2, 3) ZSerror (Note 2, 4) TCV (Note 7, 13) Full-Scale Error U option W option Zero-Scale Error U option W option Ratiometric Temperature Coefficient DCP Register between 10 hex and 6F hex Monotonic over all tap positions -0.75 -1 -2 -5 0 0 -1 -1 1 1 4 0.75 1 0 0 2 5 LSB LSB LSB LSB ppm/C LSB LSB
DNL (Note 2, 5) Differential Non-Linearity INL (Note 2, 6) Integral Non-Linearity
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ISL96017
Electrical Specifications Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX UNIT
DCP IN RESISTOR MODE (Measurements between RH and RW with RL not connected) R127 (Note 8) Resistance Offset. U version - DCP Register set to 7F hex. Measured between RH and RW pins. W version - DCP Register set to 7F hex. Measured between RH and RW pins. TCR (Note 11,13) RDNL (Note 8,9) RINL (Note 8,10) Resistance Temperature Coefficient Resistance Differential NonLinearity Resistance Integral Non-Linearity -0.75 -1 0 0.5 1 100 0.75 1 2 5 MI MI ppm/C MI (Note 1) MI (Note 1)
EEPROM SPECS EEPROM Endurance EEPROM Retention tWC (Note 12) Non-Volatile Write Cycle Time SERIAL INTERFACE SPECS VIL VIH Hysteresis VOL Cpin fSCL tIN tAA tBUF WP, SDA, and SCL Input Buffer LOW Voltage WP, SDA and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 4mA WP, SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs. SCL Falling Edge to SDA Output Data Valid Time the Bus Must be Free Before the Start of a New Transmission Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VDD during the following START condition Measured at the 30% of VDD crossing Measured at the 70% of VDD crossing SCL rising edge to SDA falling edge. Both crossing 70% of VDD From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD From SCL rising edge crossing 70% of VDD to SDA entering the 30% to 70% of VDD window From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VDD 1300 -0.3 0.7* VDD 0.05* VDD 0 0.4 10 400 50 900 0.3* VDD VDD +0.3 V V V V pF kHz ns ns ns At 55C 1,000,000 50 6 12 Cycles Years ms
tLOW tHIGH tSU:STA tHD:STA tSU:DAT
1300 600 600 600 100
ns ns ns ns ns
tHD:DAT tSU:STO
Input Data Hold Time STOP Condition Setup Time
0 600
ns ns
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ISL96017
Electrical Specifications Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. (Continued)
SYMBOL tHD:STO tDH PARAMETER STOP Condition Hold Time Output Data Hold Time TEST CONDITIONS From SDA rising edge to SCL falling edge. Both crossing 70% of VDD From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window From 30% to 70% of VDD From 70% to 30% of VDD Total on-chip and off-chip MIN 600 0 TYP (Note 1) MAX UNIT ns ns
tR tF Cb Rpu
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL
20+ 0.1*Cb 20+ 0.1*Cb 10 1
250 250 400
ns ns pF k
SDA and SCL Bus Pull-Up Resistor Maximum is determined by tR and tF Off-Chip For Cb = 400pF, max is about 2~2.5k For Cb = 40pF, max is about 15~20k WP Setup Time WP Hold Time Before START condition After STOP condition
tSU:WP tHD:WP NOTES:
600 600
ns ns
2. Typical values are for TA = 25C and VDD = 3.3V. 3. LSB = (V(RW)127 - V(RW)0)/127. V(RW)127 and V(RW)0 are the voltage at pin RW for the DCP Register set to 7F hex and 00 hex respectively. 4. FSerror = (V(RW)127 - VDD)/LSB 5. ZSerror = V(RW)0/LSB 6. DNL = [(V(RW) i - V(RW) i-1)/LSB] - 1, for i from 1 to 127. i is the DCP Register setting. 7. INL = [V(RW) i - i * LSB - V(RW)0]/LSB, for I = 1 to 127. [ Max ( V ( RW )i ) - Min ( V ( RW )i ) ] 10 8. TC = ---------------------------------------------------------------------------------------------- x ---------------- for i = 16 to 111, and T = -40C to 85C V ( Max ( V ( RW )i ) + Min ( V ( RW )i ) ) 2 125C 9. MI = (R0 - R127)/127. MI is minimum increment. R0 and R127 are the resistances between RH and RW with the DCP Register set to 00 hex and 7F hex, respectively. 10. RDNL = (R i - R i-1)/MI - 1, for i from 1 to 111. i is the DCP Register setting. 11. RINL = [R i - (MI * i) - R127]/MI, for i from 1 to 111. [ Max ( Ri ) - Min ( Ri ) ] 12. TC = --------------------------------------------------------------- x 1 x 10 - ; for i = 1 to 111, and T = -40C to 85C - -----------------R [ Max ( Ri ) + Min ( Ri ) ] 2 125C 13. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 14. Parameter is not 100% tested.
6 6
I2C Timing Diagram
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
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FN8243.1 April 17, 2006
ISL96017 Typical Performance Curves
140 T = 25C 120 WIPER RESISTANCE () 100 80 60 40 20 0 0 20 40 60 80 100 TAP POSITION (DECIMAL) 120 140 DNL (LSB) VDD = 3.6V 0.15 VDD = 3.0V 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 T = 25C -0.25 0 20 40 60 80 100 TAP POSITION (DECIMAL) 120 140 VDD = 3.6V
VDD = 3.0V
FIGURE 1. WIPER RESISTANCE vs TAP POSITION FOR 10k (W)
FIGURE 2. DNL vs TAP POSITION FOR 10k (W)
0.2 T = 25C 0.15 0.1 INL (LSB) 0.05 0 -0.05 -0.1 -0.15 -0.2 0 20 VDD = 3.0V 40 60 80 100 TAP POSITION (DECIMAL) 120 140 VDD = 3.6V RDNL (LSB)
0.2 T = 25C 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 20 40 60 80 100 TAP POSITION (DECIMAL) 120 140 VDD = 3.0V VDD = 3.6V
FIGURE 3. INL vs TAP POSITION FOR 10k (W)
FIGURE 4. RDNL vs TAP POSITION FOR 10k (W)
0.4 T = 25C 0.3 0.2 RINL (LSB) 0.1 0 -0.1 -0.2 -0.3 0 20 40 60 80 100 TAP POSITION (DECIMAL) 120 140 VDD = 3.0V
VDD = 3.6V
FIGURE 5. RINL vs TAP POSITION FOR 10k (W)
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ISL96017 Principles of Operation
This device combines a DCP, 16kbit non-volatile memory, and an I2C serial interface providing direct communication between a host and the DCP and memory. controls the access to the DCP byte (See "Access to DCP Register and IVR"). Bytes at addresses 7FC hex and 7FD hex, are reserved, which means that they should not be written, and their value should be ignored if they are read. (See Table 1).
DCP Description
The DCP has 10k or 50k nominal total resistance and 128 taps. It is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP, the RH and RL pins, are equivalent to the fixed terminals of a mechanical potentiometer. The RW pin is connected to intermediate nodes, and it is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile DCP Register. When the DCP Register contains all zeroes (00 hex, or "R0"), its wiper terminal, RW, is closest to its RL terminal. When the DCP Register contains all ones (7F hex, or "R127"), its wiper terminal is closest to its RH terminal. As the value of the DCP Register increases from all zeroes to all ones, the wiper moves monotonically from the position closest to RL to the closest to RH. Therefore, the resistance between RH and RW decreases monotonically from R0 to R127, while the resistance between RW and RL increases monotonically from R127 to R0. While the device is being powered up, the DCP Register is reset to 40 hex (64 decimal). Soon after the power supply voltage becomes large enough for reliable non-volatile memory reading, the device reads the value stored on the non-volatile Initial Value Register (IVR) and loads it into the DCP Register.
Access to DCP Register and IVR
The volatile DCP Register and the non-volatile (IVR) can be read or written directly using the I2C serial interface, with Address Byte 07FF hex. The MSB of the byte at address 7FE hex is called "OnlyVolatile" and controls the access to the DCP Register and IVR. This bit is volatile and it's reset to "0" at power up. The Data Byte read from memory address 7FF hex, is from the DCP register when the "OnlyVolatile" bit is "1", and from the IVR when this bit is "0". The Data Byte of a Write operation to memory address 7FF hex is written only to the DCP Register when the "OnlyVolatile" bit is "1", and it's written to both the DCP Register and the IVR when this bit is "0". When writing to the "OnlyVolatile" bit at address 7FE hex, the seven LSBs of the Data Byte must be all zeros. Writing to address 7FE hex and 7FF hex can be done in two Write operations, or one Write operation with two Data Bytes. See next sections for interface protocol description.
Memory Description
This device contains 2048 non-volatile bytes organized in 128 pages of 16 bytes each. This allows writing 16 bytes on a single I2C interface operation, followed by a single internal non-volatile write cycle. The memory is accessed by I2C interface operations with addresses 000 hex through 7FF hex. Bytes at addresses 000 hex through 7FB hex are available to the user as general purpose memory. The byte at address 7FF hex, IVR, contains the initial value loaded at power-up into the volatile DCP Register. The byte at address 7FE hex
TABLE 1. ISL96017 MEMORY MAP
Address Data Bits Function 7FFh 0 D 6 D5 D 4 D 3 D 2 D1 D0 IVR, DCP 7FEh OV 0 0 0 0 0 0 0 Access Control 7FDh Reserved 7FCh Reserved 7FBh D 7 D 6 D5 D 4 D 3 D 2 D1 D0 General Purpose Memory
000h
Note: OV = "Only Volatile". All other bits in register 7FEh must be 0.
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FN8243.1 April 17, 2006
ISL96017 I2C Serial Interface
This device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, this device operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 7). This device responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of the Address Byte. This device also responds with an ACK after receiving each Data Byte of a Write operation. The master must respond with an ACK after receiving each Data Byte of a read operation except the last one. A valid Identification Byte contains 1010 as the four MSBs. The following three bits are the MSBs of the memory address to be accessed. The LSB of the Identification Byte is the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (See Table 2). The complete memory address location to be accessed is a 11-bit word, since the memory has 2048 bytes. The eight LSBs are in the Address Byte.
TABLE 2. IDENTIFICATION BYTE FORMAT 1 MSB 0 1 0 A10 A9 A8 R/Wb LSB
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 6). On power up, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 6). A START condition is ignored during the power up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 6). A STOP condition at the end of a Read operation, or at the end of a Write operation to volatile bytes only places the device in its standby mode. A STOP condition during a Write operation to a non-volatile byte, initiates an
SCL
SDA
START
STOP
SCL
SDA DATA STABLE DATA CHANGE DATA STABLE
FIGURE 6. VALID DATA CHANGES, START AND STOP CONDITIONS
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ISL96017
SCL FROM MASTER 1 8 9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, one or more Data Bytes, and a STOP condition (See Figure 8). After each of the bytes, this device responds with an ACK. At this time, if the operation is only writing to volatile registers, then the device enters its standby state. If one or more Data Bytes are to be written to non-volatile memory, the device begins its internal write cycle to non-volatile memory. During this cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the device enters its standby state. The memory is organized as 128 pages of 16 bytes each. This allows writing 16 bytes on a single I2C interface operation, followed by a single internal non-volatile write cycle. The addresses of bytes within a page share the same eight MSBs, and differ on the four LSBs. For example, the first page is located at addresses 0 hex through F hex, the second page is located at addresses 10 hex through 1F hex, etc. A Write operation with more than one Data Byte sends the first Data Byte to the memory address indicated by the three address bits of the Identification Byte plus the eight bits of the Address Byte, the second Data Byte to the following address, etc. A single Write operation has to stay within a page. If the Address Byte corresponds to the lowest address of a page, then the Write operation can have anywhere from 1 to 16 Data Bytes. If the Address Byte corresponds to the highest address of a page, then only one byte can be written with that Write operation. See "Access to DCP Register and IVR" for additional information.
respond to them with ACK, and instead, goes to its standby state waiting for a new START condition. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and nonvolatile registers. During a Write sequence, Data Bytes are loaded into an internal shift register as they are received. If the address bits in the Identification Byte plus the bits in the Address Byte are all ones, the Data Byte is transferred to the DCP Register at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. The STOP condition acts as a protection of non-volatile memory. Non-volatile internal write cycles are started by STOP conditions.
Read Operation
A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 9). The master initiates the operation issuing the following sequence: a START, the Identification Byte with the R/W bit set to "0", an Address Byte which contains the LSBs of the memory address, a second START, and a second Identification Byte with the same address bits but with the R/W bit set to "1". After each of the three bytes, this device responds with an ACK. Then this device transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the Read operation (issuing a STOP condition) following the last bit of the last Data Byte. The Data Bytes are from the memory location indicated by an internal pointer. This pointer initial value is determined by the address bits in the Identification Byte plus the bits in the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte.
Data Protection
The WP pin has to be at logic HIGH to perform any Write operation to the device. When WP is active (LOW) the device ignores Data Bytes of a Write operation, does not 9
FN8243.1 April 17, 2006
ISL96017
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
SLAVE ADDRESS
ADDRESS BYTE
FIRST DATA BYTE TO WRITE
LAST DATA BYTE TO WRITE
SIGNAL AT SDA SIGNALS FROM THE SLAVE
10 1 0
0
A C K A C K A C K A C K
FIGURE 8. WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
SLAVE ADDRESS WITH R/Wb=0
ADDRESS BYTE
S T A R T
SLAVE ADDRESS WITH R/Wb=1
READ A C K A C K
S T A O C P K
SIGNAL AT SDA
1010
SIGNALS FROM THE SLAVE
0
A C K A C K
1
A C K FIRST READ DATA BYTE LAST READ DATA BYTE
FIGURE 9. READ SEQUENCE
Applications Information
The typical application diagram is shown on Figure 10. For proper operation adding 0.1F decoupling ceramic capacitor to Vdd is recommended. The capacitor value may vary based on expected noise frequency of the design.
Vdd=3.3V
Vdd=3.3V Vdd=3.3V 0.1uF
Rpu
Rpu
WP SCL SDA
RH
Vcc 0.1uF
RW
Vout
RL
R2
ISL96017
R1
FIGURE 10. TYPICAL APPLICATION DIAGRAM FOR IMPLEMENTING ADJUSTABLE VOLTAGE REFERANCE
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FN8243.1 April 17, 2006
ISL96017 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 MIN 0.70 NOMINAL 0.75 0.02 0.20 REF 0.25 0.30 3.00 BSC 2.20 2.30 3.00 BSC 1.40 1.50 0.65 BSC 0.25 0.20 0.30 8 4 0.40 1.60 2.40 0.35 MAX 0.80 0.05 NOTES 5, 8 7, 8, 9 7, 8, 9 8 2 3 Rev. 3 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals.
E 6 INDEX AREA TOP VIEW B
A3 b D D2 E
// 0.10 C 0.08 C
E2 e k L N Nd
A C SEATING PLANE
SIDE VIEW
A3
D2 (DATUM B) 1 2 D2/2
7
8
6 INDEX AREA (DATUM A)
NX k E2 E2/2
3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
NX L N 8 N-1 e 5 (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE e (A1) L1 10 L 0.10 M C A B NX b
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-WEEC-2 except for the "L" min dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN8243.1 April 17, 2006

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